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HM621100A series 1048576-word 1-bit high speed cmos static ram rev. 0.0 dec. 1, 1995 description the hitachi HM621100A is a high speed 1m static ram organized as 1048576-word 1- bit. it realizes high speed access time (20/25/35 ns) and low power consumption, employing cmos process technology and high speed circuit designing technology. it is most advantageous for the field where high speed and high density memory is required, such as the cache memory for main frame or 32-bit mpu. the HM621100A, packaged in a 400-mil plastic soj is available for high density mounting. features ? single 5 v supply and high density 28-pin package (dip and soj) ? high speed access time: 20/25/35 ns (max) ? low power dissipation active mode: 350 mw (typ) standby mode: 100 m w (typ) ? completely static memory required no clock or timing strobe required ? equal access and cycle time ? directly ttl compatible all inputs and outputs ordering information type no. access time package HM621100Ap-20 HM621100Ap-25 HM621100Ap-35 20 ns 25 ns 35 ns 400-mil 28-pin plastic dip (dp-28c) HM621100Alp-20 HM621100Alp-25 HM621100Alp-35 20 ns 25 ns 35 ns HM621100Ajp-20 HM621100Ajp-25 HM621100Ajp-35 20 ns 25 ns 35 ns 400-mil 28-pin plastic soj (cp-28d) HM621100Aljp-20 HM621100Aljp-25 HM621100Aljp-35 20 ns 25 ns 35 ns
HM621100A series 2 pin arrangement a19 q 27 1 a0 2 a1 3 a2 4 a3 5 a4 6 a5 7 nc 8 a6 9 a7 10 a8 11 a9 12 13 14 v ss we v cc 28 a18 26 a17 25 a16 24 a15 23 a14 22 nc 21 a13 20 a12 19 a11 18 a10 17 d 16 cs 15 (top view) pin description pin name function a0 C a19 address d input q output cs chip select we write enable v cc power supply v ss ground
HM621100A series 3 block diagram a19 a18 a17 a16 v cc v ss memory array 512 2048 row decoder column i/o column decoder din cs we a0 dout a1 a2 a3 a4 a5 a6 a7 a8 a9 a15 a14 a13 a12 a11 a10
HM621100A series 4 function table cs we mode v cc current output pin ref. cycle h x not selected i sb , i sb1 high-z l h read i cc dout read cycle l l write i cc high-z write cycle note: x : h or l absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss vin C0.5 *1 to +7.0 v power dissipation p t 1.0 w operating temperature range topr 0 to +70 c storage temperature range tstg C55 to +125 c storage temperature range under bias tbias C10 to +85 c note: 1. vin min = C2.0 v for pulse width 10 ns. recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v v ss 000v input high (logic 1) voltage v ih 2.2 6.0 v input low (logic 0) voltage v il C0.5 *1 0.8 v note: 1. v il min = C2.0 v for pulse width 10 ns.
HM621100A series 5 dc characteristics (ta = 0 to +70 c, v cc = 5 v 10%, v ss = 0 v) HM621100A-20 HM621100A- 25/35 parameter symbol min typ *1 max min typ *1 max unit test conditions input leakage current |i li | 2.0 2.0 m av cc = max vin = v ss to v cc output leakage current |i lo | 2.0 2.0 m a cs = v ih v i/o = v ss to v cc operating power supply current i cc 150 120 ma cs = v il , i i/o = 0 ma, min cycle standby power supply current i sb 60 40ma cs = v ih , min cycle standby power supply current (1) i sb1 *2 0.02 2.0 0.02 2.0 ma cs 3 v cc C0.2 v 0 v vin 0.2 v or vin 3 v cc C0.2 v i sb1 *3 100 100 m a output low voltage v ol 0.4 0.4 v i ol = 8 ma output high voltage v oh 2.4 2.4 v i oh = C4 ma notes: 1. typical values are at v cc = 5.0 v, ta = +25 c and not guaranteed. 2. p and jp version 3. lp and ljp version capacitance (ta = 25 c, f = 1 mhz) parameter symbol min max unit test conditions input capacitance cin 5 *2 pf vin = 0 v 6 *3 output capacitance cout 8 pf vout = 0 v notes: 1. this parameter is sampled and not 100% tested. 2. soj package 3. dip package ac characteristics (ta = 0 to +70 c, v cc = 5 v 10%, unless otherwise noted.) test conditions _ input pulse levels: 0 v to 3.0 v _ input rise and fall time: 4 ns _ input timing reference levels: 1.5 v _ output timing reference levels: 1.5 v _ output load: see figures
HM621100A series 6 output load (a) output load (b) (for t hz , t lz , t wz and t ow ) note: 1. including scope and jig + 5 v 480 w 5 pf *1 255 w dout + 5 v 480 w 30 pf *1 255 w dout read cycle HM621100A- 20 HM621100A- 25 HM621100A- 35 parameter symbol min max min max min max unit read cycle time t rc 20 25 35 ns address access time t aa 20 25 35 ns chip select access time t acs 20 25 35 ns chip selection to output in low-z t lz *1 555 ns chip deselection to output in high-z t hz *1 0 10 0 12 0 15 ns output hold from address change t oh 555 ns chip selection to power up time t pu 000 ns chip deselection to power down time t pd 12 15 25 ns note: 1. transition is measured 200 mv from high impedance voltage with load (b). this parameter is sampled and not 100% tested. read timing waveform (1) ( we = v ih , cs = v il ) t rc address t aa t oh dout valid data t oh
HM621100A series 7 read timing waveform (2) *1 ( we = v ih ) t rc t acs t lz t pu high-z 50% valid data t pd 50% high-z t hz cs dout v cc supply current i cc i sb note: 1. address valid prior to or coincident with cs transition low. write cycle HM621100A-20 HM621100A-25 HM621100A-35 parameter symbol min max min max min max unit write cycle time t wc 20 25 35 ns chip selection to end of write t cw 15 17 25 ns address valid to end of write t aw 16 20 30 ns address setup time t as 000ns write pulse width t wp *2 15 17 25 ns write recovery time t wr *3 000ns write to output in high-z t wz *1 012015015ns data to write time overlap t dw 12 15 20 ns data hold from write time t dh 000ns output active from end of write t ow *1 000ns output hold from address change t oh *4 555ns notes: 1. transition is measured 200 mv from high impedance voltage with load (b). this parameter is sampled and not 100% tested. 2. a write occurs during the overlap of a low cs and a low we . 3. t wr is measured from the earlier of cs or we going high to the end of write cycle. 4. dout is the same phase of write data of this write cycle, if t wr is long enough.
HM621100A series 8 write timing waveform (1) ( we controlled) address cs we dout din t wc t cw t aw t as t dw t dh t wz high-z t ow t wr t wp t oh valid data
HM621100A series 9 write timing waveform (2) ( cs controlled) address cs we dout din t wc t aw t as t cw t wr t wp t dw t dh valid data high-z *1 note: 1. if the cs low transition occurs simultaneously with the we low transition or after the we transition, the output buffers remain in a high impedance state. low v cc data retention characteristics (ta = 0 to +70 c) this characteristics is guaranteed only for l-version. parameter symbol min typ max unit test conditions v cc for data retention v dr 2.0 v cs 3 v cc C0.2 v, vin 3 v cc C0.2 v or 0 v vin 0.2 v data retention current i ccdr 2 50 *1 m a chip deselect to data retention time t cdr 0ns operation recovery time t r 5ms note: 1. v cc = 3.0 v
HM621100A series 10 low v cc data retention timing waveform v cc cs 4.5 v 2.2 v v dr 0 v t cdr data retention mode t r cs 3 v cc ?.2 v 4.5 4.75 5.0 5.25 5.5 0.7 0.8 0.9 1.0 1.1 1.2 1.3 low level input voltage v (normalized) supply voltage vcc (v) il ta=25? low level input voltage vs. supply voltage 4.5 4.75 5.0 5.25 5.5 0.7 0.8 0.9 1.0 1.1 1.2 1.3 high level input voltage v (normalized) supply voltage vcc (v) ih ta=25? high level input voltage vs. supply voltage
HM621100A series 11 12345 0.4 0.6 0.8 1.0 1.2 1.4 1.6 high level output current i (normalized) high level output voltage v (v) oh oh ta=25? vcc=5v high level output current vs. high level output voltage 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 0.2 0.4 0.6 0.8 low level output current i (normalized) low level output voltage v (v) ol ol ta=25? vcc=5v low level output current vs. low level output voltage 10 10 10 10 020406080 -4 -5 -6 -7 standby current i (a) ambient temperature ta (?) sb1 vcc=3v cs=2.8v standby current vs. ambient temperature
HM621100A series 12 2345 6 0.2 0.4 0.6 0.8 1.0 1.2 1.4 standby current i (normalized) supply voltage vcc (v) sb1 ta=25? cs=vcc-0.2v standby current vs. supply voltage 4.5 4.75 5.0 5.25 5.5 0.4 0.6 0.8 1.0 1.2 1.4 1.6 supply current icc (normalized) supply voltage vcc (v) ta=25? supply current vs. supply voltage 0 20406080 0.4 0.6 0.8 1.0 1.2 1.4 1.6 supply current icc (normalized) ambient temperature ta (?) vcc=5.0v supply current vs. ambient temperature
HM621100A series 13 4.5 4.75 5.0 5.25 5.5 0.7 0.8 0.9 1.0 1.1 1.2 1.3 access time t ,t (normalized) supply voltage vcc (v) acs aa ta=25? access time vs. supply voltage 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 50 100 150 200 access time t ,t (normalized) load capacitance c (pf) l aa acs access time vs. load capacitance access time t ,t (normalized) ambient temperature ta (?) aa acs 0204060 80 0.7 0.8 0.9 1.0 1.1 1.2 1.3 vcc=5.0v access time vs. ambient temperature
HM621100A series 14 010 3040 50 0.2 0.4 0.6 0.8 1.0 1.2 1.4 supply current icc (normalized) frequency f (mhz) 20 100 33 25 20 50 t (ns) supply current vs. frequency
HM621100A series 15 package dimensions HM621100Ap/alp series (dp-28c) unit: mm
HM621100A series 16 HM621100Ajp/aljp series (cp-28d) unit: mm

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